CPU architecture

How do computers actually work? We learn about the internals of a CPU, the fetch-decode-execute cycle, primary memory, and how binary represents information (plus a lot more).
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Maj123
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CPU architecture

Post by Maj123 » 22 Sep 2018, 19:44

Hello,
I was reviewing the Instruction Cycle, but I got confused on the "decode" step. In the 'fetch' phase, the Control Unit copies the value from the Memory Data Register onto the Current Instruction Register. However, in the 'decode' step, the decoder interprets the instruction inside the Instruction Register and not the Current Instruction Register. I don't quite understand the difference between the Instruction Register and Current Instruction Register. Thanks!
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Mr. MacKenty
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Re: CPU architecture

Post by Mr. MacKenty » 23 Sep 2018, 09:50

Hello Maj123!

During the Fetch-Decode-Execute-Store cycle, the CPU is actually managing two different things from primary memory: the address and the instruction (or data).

You ask:
I don't quite understand the difference between the Instruction Register and Current Instruction Register. Thanks!
They are the same thing. From our wiki: current instruction register - stores actual instruction that is being decoded and executed. Are they listed as different somewhere? Please don't get IR - interrupt register, which manages requests from I/O devices confused with current instruction register.

Thank you for your question. Please reply and let me know if this has answered your question or if you have further questions.

Warmly,

Mr. MacKenty

Maj123 wrote:
22 Sep 2018, 19:44
Hello,
I was reviewing the Instruction Cycle, but I got confused on the "decode" step. In the 'fetch' phase, the Control Unit copies the value from the Memory Data Register onto the Current Instruction Register. However, in the 'decode' step, the decoder interprets the instruction inside the Instruction Register and not the Current Instruction Register. I don't quite understand the difference between the Instruction Register and Current Instruction Register. Thanks!
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Maj123
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Posts: 10
Joined: 17 Sep 2018, 10:14

Re: CPU architecture

Post by Maj123 » 23 Sep 2018, 11:48

Thank you, that answered my question, but now I don't quite understand the function of the Interrupt Register. I understand that the IR has a role in the fetch-decode-execute cycle however, for example, this site https://tools.withcode.uk/cpu/ does not mention the IR. The IR manages requests from on/off devices, but I don't quite understand what that means.
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Mr. MacKenty
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Answers: 3

Re: CPU architecture

Post by Mr. MacKenty » 23 Sep 2018, 18:13

Hello Maj123!

I/O is short for input and output. When I think of input devices, I think of:
  • keyboards (send input to the computer when you press a key)
  • mice (send input to computer when you move the mouse)
  • microphone (send input to the computer when it is active)
  • camera (sends input to computer when it is active)
  • if you have a touch screen, it also would send data to the computer
  • input from a network might be classified as input
On the other hand, output is:
  • sound from speakers
  • output to a display (screen)
  • output to a printer
  • output to a network
Here's the problem: when you move your mouse to expect to see the mouse cursor moving over the screen. And you expect to see it REALLY FAST. In fact, if you moved the mouse, and nothing happened (or it was really slow) you would think something was wrong. The same case applies to your keyboard. When you type, you expect to see letters.

So a CPU is pretty busy. We need a way to interrupt when we have a really important task. This is the job of an interrupt. When I move my mouse, it creates an electrical point of contact which sends a signal down a dedicated wire towards the CPU. This wire is eventually connected to an interrupt controller, which translates the signal to an instruction. It then falls to the interrupt register, which holds the instruction and basically tells the CPU YO! Stop the current instruction. I've got to update the position of the mouse!. This might sound like a big deal, but when you are running 4 billion instructions per second, we can fit in some interrupts!

Please reply and let me know if this clarifies your confusion.

Warmly,

Mr. MacKenty

Maj123 wrote:
23 Sep 2018, 11:48
Thank you, that answered my question, but now I don't quite understand the function of the Interrupt Register. I understand that the IR has a role in the fetch-decode-execute cycle however, for example, this site https://tools.withcode.uk/cpu/ does not mention the IR. The IR manages requests from on/off devices, but I don't quite understand what that means.
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Maj123
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Re: CPU architecture

Post by Maj123 » 23 Sep 2018, 19:57

Thank you, I understand it completely now. :D
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